eFUSE technology is commonly used to improve SRAM yield in all CMOS technology nodes. The use of tiny electrical fuses allows engineers to fix a defective part of an SRAM circuit even after front-end-of-line (FEOL) processing, back-end-of-line (BEOL) processing, and packaging. A high-current pulse is passed through the eFUSE so that it can be melted instantly and create a local open, or a high resistance, i.e., greater than 3 kilo ohms (KΩ), through electromigration. The eFUSE is then “blown,” the defective SRAM cell is disconnected from the big SRAM array, such as 16 M or 32 M, and an otherwise non-functional SRAM array becomes functional, thereby enhancing SRAM yield.
An eFUSE 101 is normally fabricated as illustrated in FIGS. 1A and 1B. A silicide 103 is formed on the polysilicon 105 of a gate stack 107 (including gate 109 and gate oxide 111) on shallow trench isolation (STI) regions 113 in the active silicon 115. The STI provides good thermal isolation due to the low thermal conductivity of STI oxide, thereby allowing the eFUSE to be blown with minimal current flow through the eFUSE. Low eFUSE current flow is necessary as it consumes less energy and generates the lowest damage to the chip structure as a result of blowing the eFUSE. In addition, the STI surrounding the eFUSE prevents eFUSE debris from forming a conducting path to neighboring materials. In contrast, an eFUSE fabricated with active bulk silicon could form a conducting path through the conducting silicon body when eFUSE debris migrates into the active silicon.
To blow a fuse, a controlled electromigration is introduced such that the top silicided (low resistance) portion of the structure becomes hollow or electrically open, i.e., shows a high resistance. Since the silicon under the silicide is undoped, it has a high resistance. Only very low current goes through resistive silicon. Therefore, the undoped polysilicon layer remains intact during the blowing of the eFUSE, and after the eFUSE is blown, the eFUSE has a high resistance.
With a HKMG CMOS, where a metal gate 109, e.g., of titanium nitride (TiN) is present in the gate stack, the thickness of the undoped polysilicon layer 105 under the silicide 103 is a critical parameter for a reliable eFUSE. If the polysilicon layer remaining after silicidation is too thin, the silicide debris created by blowing the eFUSE can create a conducting path through the TiN 109, as shown by the zone of debris 201 in FIG. 2. As a result, the shorts can prevent the desired high resistance (open) state. As a rule of thumb, for a 32 nanometer (nm) node CMOS eFUSE process, the minimum polysilicon thickness required in the gate stack before silicidation should be greater than about 60 nm, about 25 nm that are consumed by silicide and greater than about 35 nm remaining to separate the silicide from TiN to guarantee that silicide debris does not create a conducting path to the TiN. With device scaling every generation, the polysilicon thickness is becoming thinner and thinner. For example, for a 32 nm node CMOS and also for a 28 nm node CMOS, the polysilicon thickness in the gate stack is about 40 nm to about 60 nm, which is less than the minimum required for an eFUSE.
Efforts to enable an eFUSE with a thin polysilicon (or amorphous silicon) gate stack in 32 nm and 28 nm nodes technologies include an extra patterning step in which the TiN in the eFUSE region is exposed and then removed by a wet etch process. However, the dHF cleaning process used in etching the TiN causes a TiN discontinuity 301 in the polysilicon/STI divot region 303, as illustrated in FIG. 3, which leads to high gate leakage (low Toxgl) for both NMOS and PMOS transistors.
To solve the discontinuous TiN problem, a thicker TiN layer that is less susceptible to discontinuities may be utilized. However, thicker TiN metal is known to create more significant Vt-W issues, and, therefore, is not an option. The eFUSE may also be constructed using active silicon instead of the polysilicon in the gate stack. For a silicon-on-insulator (SOI) CMOS, this does not create further issues. However, for a bulk CMOS (such as a 28 nm node CMOS), because the bulk silicon substrate is a better thermal conductor than STI, it takes significantly more current to blow the eFUSE, which is undesirable. Further, an eFUSE made of active silicon on a bulk substrate has a potential to create a conducting path in the bulk silicon substrate (since there is no buried oxide layer (BOX) beneath the eFUSE to block the conducting path, as there is with SOI).
A need therefore exists for methodology enabling the formation of an eFUSE that will not create shorts when blown and that is compatible with both SOI and bulk CMOS devices, particularly for 32 nm node and 28 nm node technologies and beyond, and for the resulting device.